1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method and a device for increasing a maximum operating frequency if there is a gap between a data write command signal and a data read command signal.
2. Description of the Related Art
FIG. 1 is a schematic data input and output circuit 10 of a conventional DRAM. The input and output circuit 10 of FIG. 1 includes bit lines BLO, /BLO (“/” indicates an active low), BL2 and /BL2, memory cells MC contacting intersection points of word lines WL_A and WL_B, sensing amplifiers S/A, data input and output lines IO and /IO, equalizing circuits IO EQ for equalizing the data input and output lines IO and /IO, a data input buffer 1, and a data output buffer 3. The equalizing circuits IO EQ are activated in response to a control signal pEQ.
FIG. 2 is a block diagram of a conventional column selection circuit. The column selection circuit 20 includes a command register 21, an OR gate 23, a delay circuit 25 and a column decoder 27.
The command register 21 responds to a clock signal CK, a chip selection signal /CS, a row address strobe /RAS, a column address strobe /CAS and a write enable /WE, generates a write command signal WRITE or a read command signal READ and outputs the write command signal WRITE or read command signal READ to the OR gate 23.
The OR gate 23 logically ORs the write command signal WRITE and the read command signal READ and outputs the result to the delay circuit 25. The delay circuit 25 responds to an output signal of the OR gate 23, delays the clock signal CK for a desired time tD, and outputs the delayed signal as a timing control signal pCD to the column decoder 27. The column decoder 27 receives and decodes n column addresses A0 through A(n−1) and selects one column signal line among 2n column signal lines CSL0 through CSL(2n−1). The column decoder 27 controls the activation timing of the column selection signal line in response to the timing control signal pCD.
Referring to FIGS. 1 and 2, data is written into a memory cell as follows. If the command register 21 outputs the data write command signal WRITE in response to the command signals CK, /RAS, /CAS and /WE, the delay circuit 25 responds to an output signal of the OR gate 23, delays the clock signal CK for the desired time tD, and outputs the delayed signal as a timing control signal pCD to the column decoder 27.
If the column decoder 27 selects and activates the column selection signal line CSL0 in response to the timing control signal pCD, input data Data-in is written into a memory cell MC through the input buffer 1, the data input and output lines IO and /IO and the bit lines BLO and /BLO.
However, if the command register 21 outputs the data read command signal READ in response to the command signals CK, /RAS, /CAS and /WE and the delay circuit 25 delays the clock signal CK for the desired time tD and outputs the delayed signal as the timing control signal pCD to the column decoder 27 in response to an output signal of the OR gate 23.
If the column decoder 27 selects and activates a column signal line CSL0 in response to the timing control signal pCD, data stored in a memory cell MC is output to a sensing amplifier S/A through the bit lines BLO and /BLO, the sensing amplifier S/A amplifies the received data and outputs output data Data-out through the data input and output lines IO and /IO and output buffer 3.
FIG. 3 is a timing diagram of data input and output in a case where there is no gap between the data write command signal WRITE and the data read command signal READ, i.e., in a case where the data read command signal READ is activated within one period tCK of the clock signal CK after the data write command signal WRITE is inactivated and further a case that the data write command signal WRITE is interrupted by the data read command signal READ.
Referring to FIGS. 1 through 3, in the case where the data input and output lines IO and /IO are not equalized after the data D23 is written in the memory cells MCs, and read data Q01 stored in the memory cells MCs, since the data D23 which is remaining on the data input and output lines IO and /IO is written to the bit lines on the data Q01, data Q01 to be read is lost.
To prevent this problem, the delay time tD of the delay circuit 25 is set to be more than an equalizing time tEQ required for being equalized to the data input and output lines IO and /IO. The equalizing time tEQ is required for write-read operations which occur consecutively in a case where there is no gap between the data write command signal WRITE and the data read command signal READ as shown in FIG. 3.
FIG. 4 is a timing diagram showing data input and output lines in a case where there is a gap of one clock signal period between the data write command signal and the data read command signal. Referring to FIG. 4, a gap indicates the case where the data read command signal READ is activated after the data write command signal WRITE is inactivated and one period tCK of the clock signal. Accordingly, in the case where there is a gap, a continuous write-read operation does not require equalization time tEQ.
Referring to FIGS. 1, 2 and 4, if the delay time for activating the column selection signal line CSL after the clock signal CK is input into the column selection circuit 20 is referred to as tD, and the delay time for outputting data after the column selection signal line CSL is activated is referred to as tCA, the maximum operating frequency of an SDRAM having a CAS latency CL of 2 clock periods (2*tCK) is obtained by Equation 1.1/CK=2/(tD+tCA)  (1)
In order to increase the maximum operating frequency of an SDRAM having a CL of 2, tCA or/and tD should be decreased. Here, if tCA is fixed, tD should be decreased to increase the maximum operating frequency of the SDRAM having a CL of 2. However, tD must be more than the equalizing time tEQ.
Accordingly, since the delay time tD of the delay circuit 25 is fixed in FIG. 2, the maximum operating frequency of an SDRAM having a CL of 2 is obtained by Equation 1, regardless of whether there is a gap between the data command signal and data read command signal.
Therefore, a user cannot increase the maximum operating frequency of an SDRAM having a CL of 2 in the case of performing write-read operations in order.